After teasing us this summer, Imagination is ready to provide full details of its first Warrior CPU core. Its new P5600 design centers on the MIPS Series5 architecture, which brings performance upgrades like 128-bit SIMD (single instruction, multiple data) code support, hardware virtualization and numerous low-level optimizations. The design reportedly manages brisk 32-bit performance in a considerably smaller footprint than rivals -- a P5600 occupies about 30 percent less space than a "comparable" Exynos 5 Octa, Imagination says. It may be a long while before we see that speed in a smartphone, however. The company will start licensing the core this quarter, but customers still have to build processors and ship finished devices.
Imagination reveals first MIPS 'Warrior P-class' CPU core
Featuring 128-bit SIMD and hardware virtualization with industry-leading 32-bit performance in 30% smaller area than competition
London, UK – 14 October, 2013 – Imagination Technologies (IMG.L), a leading multimedia, processor, communications and cloud technologies company, announces the first MIPS Series5 'Warrior P-class' CPU, representing a major step forward in feature set for high-performance MIPS CPU IP cores. The new MIPS P5600 core delivers industry-leading 32-bit performance together with class-leading low power characteristics in a silicon footprint up to 30% smaller than comparable CPU cores, making it ideal for a wide range of mobile, consumer and embedded applications.
The MIPS P5600 incorporates key features needed for today's leading-edge processors, which demand advanced features such as support for multiple security contexts, large address spaces and advanced SIMD processing:
· Full 128-bit SIMD designed for high performance on data parallel operations such as DSP, imaging and media
· Simple, flexible and complete hardware virtualization
· Next-generation security to address modern media delivery requirements
· Support for up to six cores per cluster with high-performance cache coherency
· Advanced addressing:
o Enhanced Virtual Addressing (EVA) enables more flexible usage of virtual address space, allowing for easy and efficient use of memory for larger footprint Linux implementations
o Extended Physical Addressing (XPA) allows a 32-bit system to access physical memory beyond the 32-bit limit, up to 1 Terabyte (40-bits)
Building on this first important milestone in the new MIPS Series5 era, the MIPS 'Warrior' family of CPUs will expand over the next 12 months to comprise a compelling portfolio of 64-bit and 32-bit variants, each delivering best-in-class performance, and benefiting from the unrivalled MIPS architecture that enables seamless migration from 32-bit to 64-bit solutions.
Says Tom R. Halfhill, a senior analyst with The Linley Group and a senior editor of Microprocessor Report: "As the first new MIPS core introduced since the acquisition of MIPS Technologies, the MIPS P5600 shows that Imagination Technologies is pushing the historic MIPS architecture forward. It's the first MIPS core to implement the MIPS Release 5 ISA, which includes important features like the MIPS SIMD Architecture and virtualization. We're looking forward to seeing the rest of the MIPS Warrior family rolled out over the next year."
With the P5600, Imagination is offering a compelling CPU suitable for a broad range of products targeting a balance of high-performance processing with small silicon area and excellent low power credentials. The P5600 supports multicore configurations of up to six cores per cluster with high-performance cache coherency, hardware virtualization, 128-bit SIMD, plus significant microarchitecture optimizations for maximizing SoC system performance. The P5600 is ideal for SoCs targeting next-generation mobile phones and tablets, connected consumer products such as set-top boxes, DTVs and multiroom multi-channel audio systems, home and office networking and micro-servers.
Tony King-Smith, EVP marketing, Imagination, says: "We are proud to announce this first MIPS 'Warrior P-class' CPU. This is about much more than the arrival of yet another CPU IP core. This is the start of something much bigger – the rollout of a comprehensive family of next-generation CPUs that will change the CPU IP landscape forever. As we continue to roll out MIPS Series5 products to address the applications spectrum from entry-level to the high-end, we will provide levels of performance, efficiency and functionality that surpass other offerings in the market. Many more Warriors are coming!"
MIPS P5600 by the numbers:
· Achieves industry-leading high-end CPU IP performance exceeding 5 CoreMark/MHz with 3.5 DMIPS/MHz*
· Silicon footprint up to 30% smaller than competing IP cores**
· Can implement to a very wide range of performance, power and area footprints spanning 1GHz to above 2GHz***
Hardware virtualization: system reliability, scalability and robustness
The P5600 cores are the first MIPS CPU IP cores to include highly-optimized hardware virtualization as defined in the MIPS r5 architecture announced December 2012. The industry already uses virtualization technology extensively in applications for servers, automotive and other products requiring the use of multiple secure and isolated operating systems. Imagination is taking this concept to the next level, leveraging virtualization as the foundation for a growing number of applications demanding robustness, support for multiple security contexts and more. Starting with the P5600, MIPS Series5 cores embrace hardware virtualization from the entry level to the high end, with simple, flexible and complete virtualization across the MIPS Series5 range.
Next generation security
In a fully connected world with modern media delivery requirements, security needs have outgrown traditional methodologies. The P5600 core is optimized to support multiple security contexts, leveraging technology from Imagination and ecosystem partners for mobile, connected consumer, IoT and other segments. The platform scales to support secure content delivery, secure payments, identity protection and more across multiple applications and content sources.
128-bit SIMD: higher data-parallel system performance
The P5600 is the first MIPS CPU core to feature full 128-bit SIMD support, delivering the highest performance for a wide range of tasks that can exploit the efficiencies of SIMD execution in data-parallel applications such as audio codecs, image processing, DSP, low-level simple 2D graphics and other media-rich applications. The SIMD engine used in the P5600 supports a wide variety of data types from 8-bit integer up to native double precision floating point operations.
The MIPS SIMD architecture adheres to true RISC philosophy, starting with thirty-two 128-bit architectural registers. Instructions were defined to be easily supported within high-level languages such as C or OpenCL for fast and simple development of new code, as well as leverage of existing code. The hardware-efficient, compiler-friendly implementation of the SIMD in the P5600 is perfectly aligned with the industry's shift toward code portability using JITs and other forms of dynamic compilers.
Extensive optimizations throughout
With the P5600, Imagination has also implemented a range of performance enhancing features compared to earlier generations of MIPS cores, including widened datapaths and buses, increased L2 cache prefetching, enhanced load/store bonding, and optimizations for JIT and browser applications.
In addition, the P5600 incorporates Enhanced Virtual Address (EVA) and Extended Physical Address (XPA) features that enable scalability to future generations of products. EVA enhances the effective use of the virtual memory space in the P5600, allowing both user and kernel space to access more than 3GB of space each without the need for HIGHMEM support in Linux. XPA extends the physical addressing capabilities of the P5600 up to 1 Terabyte. In combination with hardware virtualization, EVA and XPA extend the usability of the P5600 well beyond other 32-bit CPUs.
MIPS: the ultimate 64/32-bit architecture
The MIPS architecture enables binary compatibility across the range of Series5 Warrior CPUs, delivering superior performance and efficiency from entry-level/microcontroller CPUs up to high-end performance-driven networking systems. MIPS Series5 cores share a common datapath for execution of all 32-bit and 64-bit code, ensuring that 32-bit binaries for any 'Warrior' CPU will run without change on any 64-bit 'Warrior' CPU. MIPS Series5 64-bit CPUs do not need any separate datapaths to run legacy 32-bit applications, eliminating wasted silicon area and power when migrating to 64-bit.
Complementing the true instruction set compatibility of MIPS, a consistent and comprehensive toolchain across 'Warrior' CPUs enables fast, easy development and debugging. Imagination is undertaking an extensive program of toolchain development, including state-of-the-art gcc and proprietary compilers, as well as significant enhancements to Imagination's popular Codescape debuggers, resulting in not only a choice of toolchains to suit every developer environment, but also growing support for heterogeneous debugging.
The P5600 will be available for licensing this quarter. When MIPS IP cores are combined with Imagination's broad portfolio of other IP cores including PowerVR graphics and video, Ensigma radio communications, FlowCloud IP and more, Imagination's customers have a complete solution for their connected SoCs.
Presentation at Linley Tech Processor Conference
Imagination's director of processor technology marketing Mark Throndson will present technical details about the MIPS P5600 CPU family at the 2013 Linley Tech Processor Conference in Santa Clara, California. Mr. Throndson's presentation, "Enter the Warrior," will take place at 10:55 a.m. Pacific on Thursday, 17th October. For more information and to register, visit www.linleygroup.com.
About MIPS processors
Imagination's family of MIPS processors are ideal for products where ultra low-power, compact silicon area and a high level of integration are required. MIPS processor IP cores and architectures range from tiny 32-bit microcontrollers to 32-bit and 64-bit multi-core solutions for advanced application and network processing platforms.
Based on a heritage built and continuously innovated over more than three decades, Imagination's MIPS architecture is the industry's most efficient RISC architecture, delivering the best performance and lowest power consumption in a given silicon area. SoC designers can use this efficiency advantage for significant cost and power savings, or to implement additional cores to deliver a performance advantage in the same power, thermal and area budget.
The CPU IP cores comprising the MIPS Series5 'Warrior' family will come in three classes of performance and features:
· 'Warrior M-class': entry-level MIPS cores for embedded and microcontroller applications, a progression from the popular microAptiv family
· 'Warrior I-class': mid-range, feature-rich MIPS CPUs following on from the highly-efficient interAptiv family
· 'Warrior P-class': high-performance MIPS processors building on the award-winning proAptiv family
* Performance metrics based on preliminary P5600 core RTL as well as proAptiv core using gcc 4.9.0 compiler; comparisons based on publicly available information from ARM, CoreMark scores from EEMBC CoreMark website, and material available on the Internet
** Comparison based on publicly available information from Samsung's ISSCC presentation on its Exynos 5 Octa
*** TSMC 28nm process