4: All the companies are banking on embeding the chip into all of their home electrnci eventualy, since it is designed to communicate with itself(and other chips that have the ability) via a 3.9gb/s dedicated BUS architecture. So the more things they put it in..the better they can 'intergrate' the enviorment having all cell based devices share a common 'language' of sorts..that was the original business plan as I remember hearing it last year :-)
5: The cell proccessor is a multi-core in-order unit chip. That contains one multi-purpose control unit (PPU) and 8 in-order spetializable sub-cores (SPUs) all running at 3.2~3.4ghz(on the current gen of it anyways, they plan to raise this later on as technology improves). With a high on dye dedicated bus and a 3.9gb/s dedicated chip com bus, which assists in the communication structure. The chips can be easily 'beowulfed' of sorts together via this bus since they all communicate commonly, so one can pass programs of to another. The PPUs (which usualy toss the programs/datasets to SPUs for proccessing) link up and share tasks..It's really quite an ingenious architecture (imho). On the ps2 for example, the cell and RSX use the bandwidth(though they don't share a PPU to PPU communication structure) they do share other things ;-)..
Reader Comments (Page 1 of 1)
Alexei K. @ Jan 12th 2006 1:15PM
4: All the companies are banking on embeding the chip into all of their home electrnci eventualy, since it is designed to communicate with itself(and other chips that have the ability) via a 3.9gb/s dedicated BUS architecture. So the more things they put it in..the better they can 'intergrate' the enviorment having all cell based devices share a common 'language' of sorts..that was the original business plan as I remember hearing it last year :-)
5: The cell proccessor is a multi-core in-order unit chip. That contains one multi-purpose control unit (PPU) and 8 in-order spetializable sub-cores (SPUs) all running at 3.2~3.4ghz(on the current gen of it anyways, they plan to raise this later on as technology improves). With a high on dye dedicated bus and a 3.9gb/s dedicated chip com bus, which assists in the communication structure. The chips can be easily 'beowulfed' of sorts together via this bus since they all communicate commonly, so one can pass programs of to another. The PPUs (which usualy toss the programs/datasets to SPUs for proccessing) link up and share tasks..It's really quite an ingenious architecture (imho). On the ps2 for example, the cell and RSX use the bandwidth(though they don't share a PPU to PPU communication structure) they do share other things ;-)..
Hope this helps!