AMD announces 6- and 12-core Opterons
By Nilay Patel 
posted May 8th 2008 2:01AM
posted May 8th 2008 2:01AM
AMD may be busy sorting out issues with its quad-core Phenoms and hard at work on "completely different" chip architectures, but that isn't stopping the company from aggressively updating its roadmap, announcing today plans for 6- and 12-core server-grade Opterons. Both the new 6-core chip, codenamed Sao Paulo, and the 12-core unit, codenamed Magny-Cours, are based on a brand-new platform called "Maranello," and slotting in to replace the planned 8-core Barcelona chip, which appears to have been canceled. According to AMD, 12-core chips are easier to manufacture, so it's going to skip over 8-core chips and go straight to the good stuff. That must be news to Intel, which is planning on shipping 8-core Nehalem chips later this year, and will probably then hold the coveted "number-of-cores" crown until AMD releases the 12-core chips in 2010. There's no word on whether any of these chips can make these processor roadmaps comprehensible or even chronological, but we can dream, can't we?[Via TG Daily]
Two, no, 6, no, 12, Baker's dozen
You know I'm crazy 'bout these AMDs couzin
You just made my day!
AMD is getting trounced right now but I'm still rooting for them. I hope they can come through in the clutch and bring us back to the days of true competition.
I am curious to know the reasoning on how 12 cores is easier than 8. I'm guessing interconnect issues.
The 12-core chip will just be two 6-core chips in the same package. (Much like how the current core 2 quads are just dual 2-core chips on the same package).
The 8-core chip will be a native octo-core (a single 8-core chip). Therefore it will be harder to manufacture than the single 6-core.
Think of it as growing 4 leaf clovers. It would be easier to grow a bunch of 3 leaf clovers, ripping off a leaf to make it a 2 leaf clover and gluing two of them together. Rather than trying to pick out the 4 leaf clovers.
Yea, well I figured that they planned 8 core as being two quads on a single die. I didn't realize they were going to try and make it a true octa. That makes sense then. I do wonder why they don't just make a dual quad as a spacer until the 12s roll out, its not exactly a major jump in manufacturing or gate array logic or anything. The interconnects are pretty standardized technology, just open up more paths for the extra core communications.
When I read this it makes me think they are going to just use 4 of their quad-cores with only 3 working cores and 1 failed core (like the 3 core Phenoms) to improve yields and have something a little more symmetrical for interconnects. Any news on this not being the case?
the current AMD quad cores are "native", not two dies in a single package.
Exactly, which is why I figured an octa spin off would be of little difficulty to implement so why not do it as a placeholder until the 12s come out? That's why I'm wondering if they are having interconnect issues, though I would be surprised of that. It just seems counter intuitive.
12 has so many divisors... 4 tri-cores, 3 quad-cores, 2 six-cores... That should be enough options to maximise the manufacturing yields...
magny-cours.
best codename ever.
if you switch the letters around a lil you get many-cougrs... which sounds like a sketchy bar in a back ally where you know you can get some ladies of the night.
Doesn't it seem likely that these things are going to need insanely fast memory and front-side busses in order to avoid being memory-starved, when there are that many processors competing for memory access?
It was this sort of massive parallelism that led BBN to build the Butterfly switch, just to allow lots and lots of processors to get at memory back when memory wasn't all that innately fast. No one could figure out how to reliably program that monster back then either, which is why you don't see its children around today.
Frankly I don't see FSBs and memory getting all that much faster in just two years.
amd has dual channel memory access
nehalem has 3 channel memory access
pa semi has 4 channel memory access
per socket.
also amd's quad cores are 4 channels of memory access per socket. 4 channels is 128-bit access, and the upcoming shanghai should be running with ddr3. theres a crossbar joining the memory, cpu, and HT links.
ddr3 is also the plan for nehalem, which has 3 channels memory access for up to 6 cores.
ddr3 could well reach 2GHz, and thats pretty damned fast. it would make shanghai 32 (GByte/second)/socket and nehalem 24 (GByte/second)/socket.
gddr5 is supposedly less demanding, that will probably scale up to similar speeds and get pressed into being used on cpus at some point, but really the main advancement going forwards will be more sockets that provide more channels.
for comparison, a quad socket 2GHz-ram nehalem would be the same 100GByte/second as the nvidia 8800 ultra, also at 100GByte/second, from 6 dual-channel worth of ram bandwidth running at 2160 MHz.
Hopefully by the time gddr5 is ready for CPUs memristors will be utilized for memory purposes. It's not likely but it sure would be nice =D
So what? The aggregate speed of the memory system itself is what matters. All those memory channels do no good at all if the overall memory system can't keep up.
the first Nehalem chips are 6 core too
true story
On man, I have ignored AMD for years when Intel took back the advantage (IMO) some years ago. I am going to wait until Intel Octacon, err I mean Octacore chips are released and see what difference they have with the AMD 6-core chips in terms of virtualization and running multiple processes in general. Whichever has the best price to performance ratio (giving in a few other factors as well) is what I'll rebuild my main home server/development box with.
Exciting time, Moore's Law seems to be on some kind of candy-induced hyperactive juice.
"...and slotting in to replace..."
wow, i was wondering when someone was going to re-introduce slot based cpu's.
*looks over at pile of outdated dual p3 motherboards*
Now if we could only have a OS that would use the power of all these cores!
The funny thing is that eventhough they manage an 12-core cpu, all intel has to do is come with a physically 8-cored cpu to beat them due to the "hyper threading" (simultaneous multithreading) which shows two cores in the OS per real core. So AMD better be having some SM implementation or they're always going ti get beat by the ghost cores of Intel. If this is planned for 2010 I think Intel will be looking at having 32 cores insode of the OS by then, so this was good news untill that 2010 date popped up.
Sorry to say this, as I used to really like AMD processors, but their 6-core Nehalem chip prolly gets beaten silly by an Intel C2D, and their 12-core prolly does no better than a Intel Quad.
Doubling/tripling the number of cores on a chip won't save Nehalem; multi-core is largely irrelevant in real world operations, a faster dual-core is a better investment than a slower 8 or 12 or 16-core processor.
Humans make mistakes so I won't diss you for it. But Nehalem is actually the next generation from Intel not from AMD.
broli:
You're absolutely right, I had a major mind-fart there.
wow I can have a chip with 12 cores, all that processing power that will never be used because applications and the OS can't see them. What's the point again other than a marketing gimmick?
About the only thing these chips would be good for is rendering if the appliaction can split duty.
Well the upside to this story is that the planned chips are going to be based on an entirely new chip architecture. Did I read that right? While AMD's stuff they announced a couple years back sounded promising, it hasn't really turned out to be that affective. So having a new architecture sounds promising....fresh start!
The race for core supremacy continues. Next they'll be counting in gigacores.