Manufacturers have been murmuring
about 3D memory chips for years, but an escalation in recent radio chatter suggests the technology is on the cusp of becoming commercial. Intel unveiled a Hybrid Memory Cube
(HMC) at IDF, which promises seven times the energy efficiency of today's DDR3, and now IBM and Micron have shown their hand too. The pair just struck up a partnership to produce cubes using layers of DRAM connected by vertical conduits known as through-silicon vias (TSVs). These pillars allow a 90 percent reduction in a memory chip's physical footprint, a 70 percent cut in its appetite for energy, and -- best of all -- a radical increase in bandwidth: HMC prototypes have already scored
128GB/s, which makes 6Gb/s SATA III look like a bottleneck. It certainly sounds like a game-changer, unless of course some rival technology like ferroelectric memory
gets there first.
Doh, sorry for the wrong caps, which were shrunken by a factor of eight. For comparison, current high-level DRAM delivers around 12.8GB/s.