Toshiba, IBM, Samsung and others in pact with the 32-nm devil
By Thomas Ricker 
posted Dec 18th 2007 3:12AM
posted Dec 18th 2007 3:12AM
Toshiba just announced its membership in an alliance to develop system chips using 32-nm circuitry. That's well below the existing 45-nm processes used in manufacturing Intel's Penryn, for example. The alliance includes IBM, AMD, Samsung (already pushing 30-nm NAND), Infineon, Freescale, and Singapore's Chartered Semiconductor Manufacturing. No surprise really, what with Tosh already in bed with IBM to develop chips using 32-nm processes. The agreement is good until 2010 and covers design, development, and the production of the itty bitty circuitry. A move which should reduce manufacturing costs for the alliance with the savings passed along to us consumers.
Good to see a bit of team work from time to time, shared R&D on something so complex and expensive yet will have a huge net benefit for both manufactures and consumers can only be a good thing :D.
Well, 32 nm, that's a whole 59 silicon crystal lattices across.
I'm really impressed with all the companies mentioned for sharing R&D like this. I wish more companies could team up, in the end it will be us consumers that see the benefits. I hope that before 2010 is up we'll see a whole host of 32nm chips.
Whats the benefits of a 32nm vs. a 45nm?
The same benefit of every die shrink, it uses less 'material' (in the old days that used to be silicon but due to quantum laws the usefulness of silicon breaks down at smaller than 45nm) therefore costs less for the manufacturer. It also uses less power, so can be more economical, it produces less heat (which is related to it using less power) so clock speeds can be ramped up.
All in all, very useful.
The numbers refer to the minimum metal pitch and width, and the minimum gate length. For each generation it's reduced by a factor of 0.707; which is the square root of 2 divided by 2. Thus if everything shrunk you'd have a die with half the area. That would mean twice as many die on a wafer, so they'd cost about half as much. But the baseband modem for a cell phone costs about $15, so it won't translate into any real savings for the phone buyer. Also any cost reduction is mostly kept by the company selling the chip, to recover development expenses.
The smaller geometry is much leakier and thus takes much more power, contrary to the other comment. Design teams go to great lengths to come up with power-reducing techniques to try to keep the power requirement of the smaller geometry close to that of the last one. When the metal lines get closer together, the capacitance increases, which increases the current needed to drive the lines. The shorter gate length and thinner gate oxide also require more current.
People have picked up on these numbers and discuss them in computer CPUs, video game processors, phone basebands, etc., but really they don't provide any benefit to the consumer. And 32 nm is still Silcon.
I'm so glad to see AMD's name on that list.
Me too. Intel being so far ahead of AMD gives me the creeps. The battle between these two is what keeping the price/performance ratio of processors on the Light Side.
Penryn reference was misplaced seeing as how that 45nm chip is in production. On the 32nm side Intel's already produced SRAM at 32nm and currently has a 32nm CPU scheduled to launch in 2009. The CPU is codenamed Westmere and is the die shrink of Nehalem. Looking a little bit further down the line, they also have 22nm scheduled to 2011, if the stay on track expect to see 32nm SRAM at the fall IDF next year.
Instructive comments like these make engadget worth reading.
Agreed. The commentators are the true informative bloggers ;)
Pretty amazing. I wonder how much smaller they can shrink these things.