The same benefit of every die shrink, it uses less 'material' (in the old days that used to be silicon but due to quantum laws the usefulness of silicon breaks down at smaller than 45nm) therefore costs less for the manufacturer. It also uses less power, so can be more economical, it produces less heat (which is related to it using less power) so clock speeds can be ramped up.
The numbers refer to the minimum metal pitch and width, and the minimum gate length. For each generation it's reduced by a factor of 0.707; which is the square root of 2 divided by 2. Thus if everything shrunk you'd have a die with half the area. That would mean twice as many die on a wafer, so they'd cost about half as much. But the baseband modem for a cell phone costs about $15, so it won't translate into any real savings for the phone buyer. Also any cost reduction is mostly kept by the company selling the chip, to recover development expenses.
The smaller geometry is much leakier and thus takes much more power, contrary to the other comment. Design teams go to great lengths to come up with power-reducing techniques to try to keep the power requirement of the smaller geometry close to that of the last one. When the metal lines get closer together, the capacitance increases, which increases the current needed to drive the lines. The shorter gate length and thinner gate oxide also require more current.
People have picked up on these numbers and discuss them in computer CPUs, video game processors, phone basebands, etc., but really they don't provide any benefit to the consumer. And 32 nm is still Silcon.
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Whats the benefits of a 32nm vs. a 45nm?
The same benefit of every die shrink, it uses less 'material' (in the old days that used to be silicon but due to quantum laws the usefulness of silicon breaks down at smaller than 45nm) therefore costs less for the manufacturer. It also uses less power, so can be more economical, it produces less heat (which is related to it using less power) so clock speeds can be ramped up.
All in all, very useful.
The numbers refer to the minimum metal pitch and width, and the minimum gate length. For each generation it's reduced by a factor of 0.707; which is the square root of 2 divided by 2. Thus if everything shrunk you'd have a die with half the area. That would mean twice as many die on a wafer, so they'd cost about half as much. But the baseband modem for a cell phone costs about $15, so it won't translate into any real savings for the phone buyer. Also any cost reduction is mostly kept by the company selling the chip, to recover development expenses.
The smaller geometry is much leakier and thus takes much more power, contrary to the other comment. Design teams go to great lengths to come up with power-reducing techniques to try to keep the power requirement of the smaller geometry close to that of the last one. When the metal lines get closer together, the capacitance increases, which increases the current needed to drive the lines. The shorter gate length and thinner gate oxide also require more current.
People have picked up on these numbers and discuss them in computer CPUs, video game processors, phone basebands, etc., but really they don't provide any benefit to the consumer. And 32 nm is still Silcon.