--Snip--Optimized for a World of "Small is Beautiful" Devices
With its unique blend of high performance and low power consumption, the VIA Isaiah Architecture has been specifically optimized to meet the rapidly growing demand for smaller, more functional, and more stylish mobile and desktop computing and personal electronics devices that will allow people to fully enjoy the rich media content and interactivity of the broadband Internet lifestyle.
These devices range from easily portable slim and light notebooks and pocket-sized Ultra Mobile PCs and Ultra Mobile Devices with rich multimedia and wireless broadband capabilities to Small Form Factor Green PCs and Digital Entertainment Centers that combine space saving designs with minimal energy consumption.
VIA Isaiah Architecture Highlights
The VIA Isaiah Architecture has been specifically designed to deliver all the performance and features necessary for running the most demanding computing, entertainment, and connectivity applications on today's and tomorrow's Internet, including high-definition video, 3D games, imaging, and virtual worlds, within a very low power and thermal envelope that makes it ideal for small form factor mobile devices such as Mini-Notebooks and Ultra Mobile Devices. Its key highlights include the following:
64-bit Superscalar Speculative Out-Of-Order MicroArchitecture
The VIA Isaiah Architecture comprises a host of advanced architectural features, including a superscalar and out of order architecture, macro-fusion and micro-fusion functionality, and sophisticated branch prediction, that significantly improve processor efficiency and performance. In addition, it also features a full and unrestricted 64-bit instruction set with plenty of headroom to support 64-bit operating systems and applications as they become available, and a new virtual machine architecture for running systems more securely and efficiently in virtual environments.
High-Performance Computation and Media Processing
As well as support for clock speeds of up to 2GHz in initial products and a high-speed, low power Front Side Bus scalable from 800MHz up to 1333MHz, the VIA Isaiah Architecture also has a highly-efficient cache subsystem with two 64KB L1 caches and 1MB exclusive L2 cache with 16-way associativity for more effective memory optimization.
For further enhanced multimedia performance, the VIA Isaiah Architecture also integrates the world's fastest x86 processor Floating Point Unit (FPU) with the ability to execute four floating point adds and four multiplies per clock and also featuring a new algorithm that minimizes latency. Support for new SSE instructions and a 128-bit wide integer data path further boost multimedia performance.
Advanced Power and Thermal Management
To minimize energy consumption and reduce heat, the VIA Isaiah Architecture utilizes new low power circuit techniques and in addition to aggressive management of active power includes support for the new "C6" power state, in which power is turned off to the caches.
Extensive Adaptive PowerSaver™ Technology features further reduce power consumption and improve thermal management, including the unique TwinTurbo™ dual-PLL implementation, which acts like automatic transmission in permitting smooth transitions between activity states within one clock cycle, ensuring always-on service and minimize latency, as well as new mechanisms for managing the die temperature.
Scalable Upgrade to VIA C7™ Processor
The VIA Isaiah Architecture is pin-to-pin compatible with the current VIA C7 processor family, enabling OEMs and motherboard makers to transition to the new architecture smoothly, and to fulfill a wider range of market segments with a single board or system design.
VIA PadLock™ Hardware Security Features
To enhance the confidentiality, integrity, and authenticity of electronic data, the VIA Isaiah Architecture incorporates industry-leading on-die hardware cryptographic acceleration features within the VIA PadLock Security Engine, including the world's best random number generator (RNG), an AES Encryption Engine, SHA-1 and SHA-256 hashing for secure message digests for data integrity, and a new specialized "secure execution mode" that includes features such as a secure on-chip memory area and encrypted instruction fetching.