FeTRAM
Latest
The big memory cube gamble: IBM and Micron stack their chips
Manufacturers have been murmuring about 3D memory chips for years, but an escalation in recent radio chatter suggests the technology is on the cusp of becoming commercial. Intel unveiled a Hybrid Memory Cube (HMC) at IDF, which promises seven times the energy efficiency of today's DDR3, and now IBM and Micron have shown their hand too. The pair just struck up a partnership to produce cubes using layers of DRAM connected by vertical conduits known as through-silicon vias (TSVs). These pillars allow a 90 percent reduction in a memory chip's physical footprint, a 70 percent cut in its appetite for energy, and -- best of all -- a radical increase in bandwidth: HMC prototypes have already scored 128Gb/s 128GB/s, which makes 6Gb/s SATA III look like a bottleneck. It certainly sounds like a game-changer, unless of course some rival technology like ferroelectric memory gets there first. Update: Doh, sorry for the wrong caps, which were shrunken by a factor of eight. For comparison, current high-level DRAM delivers around 12.8GB/s. [Thanks, Maximilian]
Ferroelectric transistor memory could run on 99 percent less power than flash
We've been keeping an optimistic eye on the progress of Ferroelectric Random Access Memory (FeRAM) for a few years now, not least because it offers the tantalizing promise of 1.6GB/s read and write speeds and crazy data densities. But researchers at Purdue University reckon we've been looking in the wrong place this whole time: the real action is with their development of FeTRAM, which adds an all-important 'T' for 'Transistor'. Made by combining silicon nanowires with a ferroelectric polymer, Purdue's material holds onto its 0 or 1 polarity even after being read, whereas readouts from capacitor-based FeRAM are destructive. Although still at the experimental stage, this new type of memory could boost speeds while also reducing power consumption by 99 percent. Quick, somebody file a patent. Oh, they already did.
