If your interest in processor speeds doesn't extend much beyond "is it fast?" then these juicy tidbits likely aren't for you. That said, AMD is certainly getting excited about its upcoming Barcelona successor: the 45nm Shanghai. The main points of interest out of the gate are HyperTransport 3.0, which was nixed late in the game on Barcelona, and six cores, which are meant to pit the chip up against Intel's upcoming six-core Dunnington chip. Where things get really exciting is a few months after Shanghai's late 2008 debut, when AMD plans do release a twin-die version, with 12 cores of happiness connected by HyperTransport 3.0. What does all that mean? Beats us, but we hope it's fast.

Quad-core shmod-core Intel, we need 6 cores or more to keep our uh, web browsers snappy. While you're at it, how about tossing in some Simultaneous Multithreading (SMT) so that each core can process two threads at a time -- 16 simultaneous threads per 8-core processor or 32 for dual-processor, 8-core rigs. If that sounds good then you're in luck; Intel just went official with its near-term architecture plans which include the 2008 launch of a 6-core Dunnington-class server CPU platform based on Intel's 45-nm Penryn "tick" architecture. On deck is Intel's second generation Nehalem "tock" architecture with SMT and scalable from 2- to 8-cores. We're talking "dramatic" performance and energy improvements, according to Intel, from a microarchitecture bent on delivering an 8 MB level-3 cache, DDR3-800 memory support, 25.6GB per second Quickpath interconnects (so long Front Side Bus!), an integrated memory controller and optional integrated graphics to high-end servers and eventually laptops. Hear that AMD? Tick, tock goes the clock.

P.S. That's Nehalem pictured. What, can't you tell?

[Via BetaNews, thanks Mike O.]

Intel's had its new processor plans slipped out to the public thanks to Sun, according to DailyTech. Details on the 6-core (!) Xeon Dunnington, as well as the kinda-sorta hush-hush Nehalem were apparently leaked out onto Sun's public web server over the weekend, including plans for the new Xeons to overtake the company's Tigerton CPU line. The Dunnington processors will have a 16MB L3 cache shared by all six cores, and will be pin-compatible with the Tigertons, thus making integration with your Clarksboro chipset slightly less painful... by being possible. The Nehalem also got the spy treatment, with news that it will not only replace the Penryn line in Q4 '08, but will also be the first time in 18 years that Intel includes on-die memory controllers. If this sort of thing is important to you (and we think it may be) hit the read link and get all the juicy details.