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Hybrid Memory Cube receives its finished spec, promises up to 320GB per second
The Hybrid Memory Cube Consortium has been almost too patient in developing a standard for for its eponymous technology -- efforts began 17 months ago -- but it at last has more than good intentions to show for its work. Its just-published HMC Specification 1.0 lets companies build platforms and RAM with 2GB, 4GB and 8GB chips incorporating the stacked, power-efficient technology, all without compatibility jitters from other supporters. The completed spec is a scorcher when living up to its full potential, too. With eight links, a memory cube can reach a peak 320GB/s (yes, that's gigabytes) of aggregate bandwidth -- more than a hair faster than the 11GB/s we often get from existing DDR3 memory. The Consortium is teasing us with more. Although we'll have to wait until the second half of the year before HMC 1.0 products appear in earnest, the Consortium already has a next-gen blueprint due in early 2014 that should nearly double individual data link speeds (from 15Gbps to 28Gbps). While we'd like to see the group walk the walk with real products before it talks more talk, there's still a chance that some memory performance bottlenecks could vanish for a good, long while.
Microsoft joins Hybrid Memory Cube Consortium to develop new DRAM standard
Intel unveiled its Hybrid Memory Cube at IDF late last year, and there's already an alliance dedicated to standardizing and implementing the technology. Now Microsoft wants in on the action: the outfit just announced that it will lend its clout to the Hybrid Memory Cube Consortium. To jog your memory, HMC technology promises seven times the efficiency of current DRR3 memory modules and is being vaunted by Intel et al. as the solution for monster systems requiring lower power usage and higher bandwidth. Redmond's joining a well-attended party; IBM, Micron, Samsung and many others are already members of the consortium.
The big memory cube gamble: IBM and Micron stack their chips
Manufacturers have been murmuring about 3D memory chips for years, but an escalation in recent radio chatter suggests the technology is on the cusp of becoming commercial. Intel unveiled a Hybrid Memory Cube (HMC) at IDF, which promises seven times the energy efficiency of today's DDR3, and now IBM and Micron have shown their hand too. The pair just struck up a partnership to produce cubes using layers of DRAM connected by vertical conduits known as through-silicon vias (TSVs). These pillars allow a 90 percent reduction in a memory chip's physical footprint, a 70 percent cut in its appetite for energy, and -- best of all -- a radical increase in bandwidth: HMC prototypes have already scored 128Gb/s 128GB/s, which makes 6Gb/s SATA III look like a bottleneck. It certainly sounds like a game-changer, unless of course some rival technology like ferroelectric memory gets there first. Update: Doh, sorry for the wrong caps, which were shrunken by a factor of eight. For comparison, current high-level DRAM delivers around 12.8GB/s. [Thanks, Maximilian]
Intel reveals 'Claremont' Near Threshold Voltage Processor, other conceptual awesomeness at IDF (video)
Thought Intel was done busting out new slabs of The Future at IDF? Wrong. Justin Rattner, the firm's chief technology officer, just took the stage here in San Francisco in order to showcase a trifecta of new concepts, all of which were borne out of research in Intel Labs. The first, and perhaps most notable, is the Near Threshold Voltage Processor (code-named "Claremont"), which relies on novel, ultra-low voltage circuits that dramatically reduce energy consumption -- like EnerJ, but not. How so? Well, by "operating close to threshold, or turn-on voltage, of the transistors," it's able to scream when needed or scale back dramatically (below ten milliwatts) when the workload is light. If you're curious as to just how low that is, we're told that it's low enough to keep running while powered only by a solar cell the size of a postage stamp. Sadly, the research chip isn't destined to become a product itself, but Intel's hoping that the knowledge gained could lead to "integration of scalable near-threshold voltage circuits across a wide range of future products, reducing power consumption by five-fold or more and extending always-on capability to a wider range of computing devices." As for demos? A smattering of multicore / multiprocessor sessions aided Intel in upping its bragging rights, and we were informed that coding for multicore setups is "easier than the press makes out to be." The outfit also took the opportunity to release a Parallel JS engine to the open source crowd, adding data-parallel capabilities to JavaScript to purportedly "speed up browser-based services such as computer vision, cryptography, and 3D games by up to eight-fold." Furthermore, a newly revealed Hybrid Memory Cube -- complete with seven times better energy efficiency than today's DDR3 memory -- was also unwrapped. More details can be found in the links below, and we've got your unveiling video embedded just beyond the break. %Gallery-133942%
